1. Field of the Invention
This invention relates to improvements in memory architectures and methods for operating same, and more particularly, to improvements in memory architectures and operations thereof for increasing the speed of data transfers between the memory array and a cache memory associated therewith.
2. Relevant Background
During recent years, the memory industry has begun to widely use synchronous DRAMs (SDRAMs). SDRAMs have begun to be so commonplace, that often the reference to its synchronous nature is dropped, and they are referred to simply as DRAMs. However, to avoid confusion, synchronous DRAMs will be consistently referred to herein as “SDRAMs”.
As SDRAMs have developed, they have been operated at ever increasing clock speeds. The SDRAMS of the second generation were called double data rate (DDR) SDRAMs, and are now often referred to as “DDR-I” SDRAMs. In the second generation of synchronous SDRAMs, clock frequencies of 133 megahertz were common. Recently, a third new generation of synchronous SDRAMs are being defined to operate at speeds of two times or greater than DDR-I SDRAMs, and are sometimes referred to as “DDR-II” SDRAMs.
The clock frequencies presently being investigated for DDR-II SDRAMs are on the order of about 200 megahertz to 400 megahertz. Although the clock frequencies of the SDRAMs have been increasing, the actual signal delays as the signals propagate through the memory circuitry have not been concomitantly decreased. Thus, one might expect that an increased clock speed applied to an SDRAM might increase the data rate available from the SDRAM, or, alternatively, reduce the access time to the data in the SDRAM. However, the memory elements themselves in the SDRAMs are generally substantially the same, and therefore, require the same amount of access time, regardless of the clock speed. Thus, an increased clock speed generally only enables a random bit of data to be accessed in about the same time frame as devices with lower clock speeds. As a result, devices that operate at higher clock speeds merely require a larger number of clock cycles to access the data in the same time frame.
To address the goal in the design of memory devices of achieving increased random access speeds, it has been proposed to include cache memory elements in the device into which the contents of the SDRAM array may be temporarily stored prior to being delivered to the output of the memory. As used herein, the term “cache” or “cache memory” is used to refer to a data latch, register, memory, or other suitable circuit that can temporarily hold or store data read from a memory array prior to being delivered to the output of the memory. Among other things, the cache memory serves to reduce the overhead associated with the SDRAM array by allowing data access to occur while the precharge and next activation of the array is underway. This effectively speeds up the overall data rate by eliminating otherwise dead periods.
Thus, when an element from the memory array is read, it is detected by a sense amplifier that is associated with the memory cell being read, then subsequently delivered from the sense amplifier to the cache memory element that is at least temporarily associated therewith. One example of a memory array having a cache memory is shown in copending patent application Ser. No. 09/689,219, filed Oct. 11, 2000, the application being assigned to the assignee of this application, and incorporated by reference.
Today, in memory architectures, in general, and SDRAM architectures, in particular, one physical circuit layout that has been suggested includes sets of sense amplifiers alternating with memory array blocks serviced by the sense amplifiers. See, for example, U.S. Pat. No. 5,887,272, which is assigned to the assignee of this application, and which is incorporated by reference. The sense amplifiers are arranged in stripes between adjacent SDRAM array blocks. Each sense amplifier stripe may be connected to selectively service the SDRAM cells on both sides of the stripe. Thus, the sense amplifiers in a particular sense amplifier stripe may be selectively connected to selected memory cells on either the memory array located on left of the stripe, or to selected memory cells located on the right of the stripe.
Additionally, memory arrays are becoming increasingly dense. For example, SDRAM designers are under constant tension to design SDRAM circuits more densely, but at the same time, to include larger amounts of functionality in the circuit. One of the techniques that integrated circuit manufacturers have used to address these problems is to place greater and greater emphasis on multilayered structures. For example, above the active regions of the device, one or more layers of interconnecting metal or other conducting material, such as polysilicon, or the like, may be used. However, as the number of the layers increases, the planarity of the surface on which subsequent layers are formed becomes increasingly uneven. As a result, the overlying or subsequently formed structures have a tendency to be susceptible to discontinuities, due to step-like structures that form at the surface. As a result, the pitch of the interconnect structures generally cannot be designed at too low a level. (The pitch of an interconnect is regarded as the distance between an interconnect structure and its closest neighbor, plus the dimension of the interconnect itself.)
One SDRAM example is class of SDRAM devices, called the “Enhanced SDRAM,” or “ESDRAM,” which has been recently introduced by Enhanced Memory Systems, Inc of Colorado Springs, Colo. An example is the SM2603 and SM2604 Enhanced SDRAM (ESDRAM) devices, which are a 64 megabit JEDEC superset standard SDRAM. While pin, function, and timing are compatible with standard SDRAMs, they have a speed and architecture that optimizes system price-to-performance in high performance main memory, video graphics, and embedded systems.
This 64 megabit ESDRAM is a high-speed SDRAM configured as four banks of SDRAM with an SRAM row cache per bank and a synchronous interface. All inputs are registered and all outputs are driven on rising clock edges. Within each bank, the devices are organized as 4096 rows of 4096 bits each. Within each row, the 8M×8 device has 512 column address locations and the 4M×16 device has 256 column locations. Read and write accesses are accomplished by opening a row and selecting a column address location for the transaction. A “bank activate” (“ACT”) command instructs the device to open a row in one of the four banks, though all four banks may be active simultaneously. A subsequent “read” or “write” command instructs the device to read data from or write data to a specified column address location.
On a random read access, an SDRAM bank is activated and data is latched into the sense amplifiers. The sense amplifiers now hold a row of data and the row is considered open. A “read” command now causes the entire row to latch into the SRAM row cache, and the data at a specified column address location is driven out. Since the row data is latched into the SRAM row cache, the SDRAM sense amplifiers are decoupled from the data. Therefore, the SDRAM precharge time can be hidden behind a burst read from the row cache. This minimizes subsequent page miss latency. Since both precharge and row address strobe (RAS) to column address strobe (CAS) delays are hidden, the device supports an industry leading CAS latency of one at clock frequencies up to 83 megahertz, and CAS latency of two up to 166 megahertz. At 166 megahertz, all but one cycle of the next random access to any location in the same bank can be hidden. This SDRAM dramatically increases sustained bandwidth by up to two times over standard SDRAM. For interleaved burst read accesses, the entire precharge time is hidden and output data can be driven without any wait states.
Nevertheless, it may be possible to increase still further the data access time of the device.